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| ? 2009 microchip technology inc. ds39687e-page 1 pic18f2xjxx/4xjxx family 1.0 device overview this document includes the programming specifications for the following devices: 2.0 programming overview of the pic18f2xjxx/4xjxx family the pic18f2xjxx/4xjxx family devices are programmed using in-circuit serial programming? (icsp?). this programming specification applies to devices of the pic18f2xjxx/4xjxx family in all package types. 2.1 pin diagrams the pin diagrams for the pic18f2xjxx/4xjxx family are shown in figure 2-1 and figure 2-2. the pins that are required for programming are listed in table 2-1 and shown in darker lettering in the diagrams. table 2-1: pin descriptions (during pr ogramming): pic18f2xjxx/4xjxx family ? pic18f24j10 ? pic18lf24j10 ? pic18f25j10 ? pic18lf25j10 ? pic18f44j10 ? pic18lf44j10 ? pic18f45j10 ? pic18lf45j10 ? pic18f24j11 ? pic18lf24j11 ? pic18f25j11 ? pic18lf25j11 ? pic18f26j11 ? pic18lf26j11 ? pic18f44j11 ? pic18lf44j11 ? pic18f45j11 ? pic18lf45j11 ? pic18f46j11 ? pic18lf46j11 ? pic18f26j13 ? pic18lf26j13 ? pic18f27j13 ? pic18lf27j13 ? pic18f46j13 ? pic18lf46j13 ? pic18f47j13 ? pic18lf47j13 ? pic18f24j50 ? pic18lf24j50 ? pic18f25j50 ? pic18lf25j50 ? pic18f26j50 ? pic18lf26j50 ? pic18f44j50 ? pic18lf44j50 ? pic18f45j50 ? pic18lf45j50 ? pic18f46j50 ? pic18lf46j50 ? pic18f26j53 ? pic18lf26j53 ? pic18f27j53 ? pic18lf27j53 ? pic18f46j53 ? pic18lf46j53 ? pic18f47j53 ? pic18lf47j53 pin name during programming pin name pin type pin description mclr mclr p programming enable v dd and av dd (1) v dd p power supply v ss and av ss (1) v ss pground v ddcore /v cap v ddcore p regulated power supply for microcontroller core v cap i filter capacitor for on-chip voltage regulator rb6 pgc i serial clock rb7 pgd i/o serial data legend: i = input, o = output, p = power note 1: all power supply and ground pins must be connected, including analog supplies (av dd ) and ground (av ss ). flash microcontroller pr ogramming specification
pic18f2xjxx/4xjxx family ds39687e-page 2 ? 2009 microchip technology inc. figure 2-1: pic18f2xjxx/4xjxx family pin diagrams 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr ra0 ra1 ra2 ra3 v ddcore /v cap ra5 v ss osc1 osc2 rc0 rc1 rc2 rc3 rb7/pgd rb6/pgc rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 28-pin spdip, soic, ssop 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 rc0 5 4 rb7/pgd rb6/pgc rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 mclr ra0 ra1 ra2 ra3 v ddcore /v cap ra5 v ss osc1/clki osc2/clko rc1 rc2 rc3 28-pin qfn pic18f2xj1x pic18f2xj5x pic18f2xj1x pic18f2xj5x ? 2009 microchip technology inc. ds39687e-page 3 pic18f2xjxx/4xjxx family figure 2-2: pic18f2xjxx/4xjxx family pin diagrams (continued) 44-pin tqfp 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 ra3 ra2 ra1 ra0 mclr rb7/pgd rb6/pgc rb5 rb4 rc6 rc5 rc4 rd3 rd2 rd1 rd0 rc3 rc2 rc1 nc nc rc0 osc2 osc1 v ss v dd re2 re1 re0 ra5 v ddcore /v cap rc7 rd4 rd5 rd6 v ss v dd rb0 rb1 rb2 rb3 rd7 5 4 nc nc 44-pin qfn rd0 rc3 rc2 rc1 rc0 rb7/pgd rb6/pgc rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rd7 rd6 rd5 rd4 rc7 rc6 rc5 rc4 rd3 rd2 mclr ra0 ra1 ra2 ra3 v ddcore /v cap ra5 re0 re1 re2 v dd v ss osc1 osc2 rc0 rc1 rc2 rc3 rd0 rd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-pin pdip 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 mclr rb5 rb4 nc rc6 rc5 rc4 rd3 rd2 rd1 osc2 osc1 v ss av dd re2 re1 re0 ra5 v ddcore /v cap rc7 rd4 rd5 rd6 v ss v dd rb0 rb1 rb2 rb3 rd7 5 4 av ss v dd av dd ra3 ra2 ra1 ra0 rb7/pgd rb6/pgc pic18f4xj1x pic18f4xj5x pic18f4xj1x pic18f4xj5x pic18f4xj1x pic18f2xjxx/4xjxx family ds39687e-page 4 ? 2009 microchip technology inc. 2.1.1 pic18f2xjxx/4xjxx/ lf2xjxx/lf4xjxx devices and the on-chip voltage regulator pic18 f xxjxx devices have an internal core voltage regulator. on these devices (?pic18 f ? in the part num- ber), the regulator is always enabled. the regulator input is taken from the microcontroller v dd pins. the output of the regulator is supplied to the v ddcore /v cap pin. on these devices, this pin simultaneously serves as both the regulator output and the microcontroller core power input pin. for these devices, the v ddcore /v cap pin should be tied to a capacitor and nothing else. pic18 lf xxjxx devices do not have an internal core voltage regulator. on these devices (?pic18 lf ? in the part number), power must be externally supplied to both v dd and v ddcore /v cap . whether or not the regulator is used, it is always good design practice to have sufficient capacitance on all supply pins. examples are shown in figure 2-3. the specifications for core voltage and capacitance are listed in section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? . figure 2-3: conne ctions for the on-chip regulator 2.2 memory maps the pic18f2xjxx/4xjxx family of devices offers program memory sizes of 16, 32, 64 and 128 kbytes. the memory sizes for different members of the family are shown in table 2-2. the overall memory maps for all the devices are shown in figure 2-4. table 2-2: program memory sizes for pic18f2xjxx/4xjxx family devices for purposes of code protection, the program memory for every device is treated as a single block. enabling code protection, thus protects the entire code memory, and not individual segments. 2.5v v dd v ddcore /v cap v ss 2.5v v dd v ddcore /v cap v ss 3.3v (v dd = v ddcore ) (v dd v ddcore ) pic18 f 2xjxx/4xjxx devices (regulator enabled) pic18 f 2xjxx/4xjxx pic18 lf 2xjxx/4xjxx devices (regulator disabled) v dd v ddcore /v cap v ss c f 3.3v pic18 lf 2xjxx/4xjxx pic18 lf 2xjxx/4xjxx device* program memory (kbytes) location of flash configuration words pic18f24j10 16 3ff8h:3fffh pic18f44j10 pic18f24j11 pic18f44j11 pic18f24j50 pic18f44j50 pic18f25j10 32 7ff8h:7fffh pic18f45j10 pic18f25j11 pic18f45j11 pic18f25j50 pic18f45j50 pic18f26j11 64 fff8h:ffffh pic18f46j11 pic18f26j13 pic18f46j13 pic18f26j50 pic18f46j50 pic18f26j53 pic18f46j53 pic18f27j13 128 1fff8h:1ffffh pic18f47j13 pic18f27j53 pic18f47j53 * includes pic18f and pic18lf devices. ? 2009 microchip technology inc. ds39687e-page 5 pic18f2xjxx/4xjxx family the configuration words for these devices are located at addresses, 300000h through 300007h. these are implemented as three pairs of volatile memory regis- ters. each register is automatically loaded from a copy stored at the end of program memory. for this reason, the last four words (or eight bytes) of the code space (also called the flash configuration words) should be written with configuration data and not executable code. the addresses of the flash configuration words are also listed in table 2-2. refer to section section 5.0 ?configuration word? for more information. locations, 3ffffeh and 3fffffh, are reserved for the device id bits. these bits may be used by the programmer to identify what device type is being pro- grammed and are described in section 5.1 ?device id word? . these device id bits read out normally, even after code protection. 2.2.1 memory address pointer memory in the device address space (000000h to 3fffffh) is addressed via the table pointer register, which in turn, is comprised of three registers: ? tblptru at ram address 0ff8h ? tblptrh at ram address 0ff7h ? tblptrl at ram address 0ff6h the 4-bit command, ? 0000 ? (core instruction), is used to load the table pointer prior to using many read or write operations. tblptru tblptrh tblptrl addr[21:16] addr[15:8] addr[7:0] pic18f2xjxx/4xjxx family ds39687e-page 6 ? 2009 microchip technology inc. figure 2-4: memory maps for pi c18f2xjxx/4xjxx family devices (1) note 1: sizes of memory areas are not to scale. sizes of accessible memory areas are enhanced to show detail. 2: addresses, 300006h and 300007h, are unimplement ed in pic18f45j10 family devices. code memory unimplemented read as ? 0 ? configuration space 000000h 1fffffh 3fffffh 2fffffh 003fffh 007fffh 200000h 300000h 300007h (2) 3ffffeh configuration words device ids configuration space memory spaces are unimplemented or unavail able in normal execution mode and read as ? 0 ?. memory spaces are read-only (device ids) or cannot be directly programmed by icsp? (configuration words). flash conf. words pic18fx4jxx (16 kbytes) code memory unimplemented read as ? 0 ? configuration space configuration words device ids configuration space flash conf. words pic18fx6jxx (64 kbytes) code memory unimplemented read as ? 0 ? configuration space configuration words device ids configuration space flash conf. words pic18fx5jxx (32 kbytes) code memory unimplemented read as ? 0 ? configuration space configuration words device ids configuration space flash conf. words pic18fx7jxx (128 kbytes) 01ffffh 00ffffh ? 2009 microchip technology inc. ds39687e-page 7 pic18f2xjxx/4xjxx family 2.3 overview of the programming process figure 2-5 shows the high-level overview of the programming process. first, a bulk erase is performed. next, the code memory is programmed. since the only nonvolatile configuration words are within the code memory space, they too are programmed as if they were code. code memory (including the configuration words) is then verified to ensure that programming was successful. figure 2-5: high-level programming flow 2.4 entering and exiting icsp? program/verify mode entry into icsp modes for pic18f2xjxx/4xjxx family devices is somewhat different than previous pic18 devices. as shown in figure 2-6, entering icsp program/verify mode requires three steps: 1. voltage is briefly applied to the mclr pin. 2. a 32-bit key sequence is presented on pgd. 3. voltage is reapplied to mclr and held. the programming voltage applied to mclr is v ih , or essentially, v dd . there is no minimum time requirement for holding at v ih . after v ih is removed, an interval of at least p19 must elapse before presenting the key sequence on pgd. the key sequence is a specific 32-bit pattern, ? 0100 1101 0100 0011 0100 1000 0101 0000 ? (more easily remembered as 4d434850h in hexa- decimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as program/verify mode is to be maintained. an interval of at least time, p20 and p12, must elapse before present- ing data on pgd. signals appearing on pgd before p12 has elapsed may not be interpreted as valid. on successful entry, the program memory can be accessed and programmed in serial fashion. while in the program/verify mode, all unused i/os are placed in the high-impedance state. exiting program/verify mode is done by removing v ih from mclr , as shown in figure 2-7. the only require- ment for exit is that an interval, p16, should elapse between the last clock and program signals on pgc and pgd before removing v ih . when v ih is reapplied to mclr , the device will enter the ordinary operational mode and begin executing the application instructions. figure 2-6: entering program/verify mode start done perform bulk erase program memory verify program done enter icsp? exit icsp mclr pgd pgc v dd p13 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434850h p2b p2a p19 p20 01001 0000 p12 v ih v ih p1 pic18f2xjxx/4xjxx family ds39687e-page 8 ? 2009 microchip technology inc. figure 2-7: exiting program/verify mode 2.5 serial program/verify operation the pgc pin is used as a clock input pin and the pgd pin is used for entering command bits and data input/output during serial operation. commands and data are transmitted on the rising edge of pgc, latched on the falling edge of pgc and are least significant bit (lsb) first. 2.5.1 four-bit commands all instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. to input a command, pgc is cycled four times. the commands needed for programming and verification are shown in table 2-3. depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. throughout this specification, commands and data are presented as illustrated in table 2-4. the 4-bit command is shown most significant bit (msb) first. the command operand, or ?data payload?, is shown ? 2009 microchip technology inc. ds39687e-page 9 pic18f2xjxx/4xjxx family 3.0 device programming programming includes the ability to erase or write the memory within the device. the eecon1 register is used to control write or row erase operations. the wren bit must be set to enable writes; this must be done prior to initiating a write sequence. it is strongly recommended that the wren bit only be set immediately prior to a program or erase operation. the free bit must be set in order to erase the program space being pointed to by the table pointer. the erase or write sequence is initiated by setting the wr bit. 3.1 icsp? erase 3.1.1 icsp? bulk erase devices of the pic18f2xjxx/4xjxx family may be bulk erased by writing 0180h to the table address, 3c0005h:3c0004h. the basic sequence is shown in table 3-1 and demonstrated in figure 3-1. since the code-protect configuration bit is stored in the program code within code memory, a bulk erase operation will also clear any code-protect settings for the device. the actual bulk erase function is a self-timed opera- tion. once the erase has started (falling edge of the 4th pgc after the nop command), serial execution will cease until the erase completes (parameter p11). during this time, pgc may continue to toggle but pgd must be held low. table 3-1: bulk erase command sequence figure 3-1: bulk erase flow figure 3-2: bulk erase timing 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 05 6e f6 01 01 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 05h movwf tblptrl write 01h to 3c0005h movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 80h to 3c0004h to erase entire device. nop hold pgd low until erase completes. start done write 8080h to 3c0004h to erase entire device write 0101h delay p11 + p10 time to 3c0005h n 12 34 1 21516 123 pgc p5 p5a pgd pgd = input 0 0011 p11 p10 erase time 000000 12 00 4 0 1 2 15 16 p5 123 p5a 4 0000 n 4-bit command 4-bit command 4-bit command 16-bit data payload 16-bit data payload 16-bit data payload 11 pic18f2xjxx/4xjxx family ds39687e-page 10 ? 2009 microchip technology inc. 3.1.2 icsp? row erase it is possible to erase one row (1024 bytes of data), provided the block is not code-protected or erase/write-protected. rows are located at static boundaries beginning at program memory address 000000h, extending to the internal program memory limit (see section 2.2 ?memory maps? ). the row erase duration is internally timed. after the wr bit in eecon1 is set, a nop is issued, where the 4th pgc is held high for the duration of the row erase time, p10. the code sequence to row erase a pic18f2xjxx/4xjxx family device is shown in table 3-2. the flowchart shown in figure 3-4 depicts the logic necessary to completely erase a pic18f2xjxx/4xjxx family device. the timing diagram that details the ?row erase? command and parameter p10 is shown in figure 3-6. table 3-2: erase code memory code sequence figure 3-3: set wr and start row erase timing note 1: if the last row of program memory is erased, bit 3 of config1h must also be programmed as ? 0 ?. 2: the tblptr register can point at any byte within the row intended for erase. 3: if code protection has been enabled, icsp bulk erase (all program memory erased) operations can be used to dis- able code protection. icsp row erase operations cannot be used to disable code protection. 4-bit command data payload core instruction step 1: enable memory writes. 0000 84 a6 bsf eecon1, wren step 2: point to first row in code memory. 0000 0000 0000 6a f8 6a f7 6a f6 clrf tblptru clrf tblptrh clrf tblptrl step 3: enable erase and erase single row. 0000 0000 0000 88 a6 82 a6 00 00 bsf eecon1, free bsf eecon1, wr nop ? hold pgc high for time p10. step 4: repeat step 3, with address pointer incremented by 1024, until all rows are erased. 12 34 1 2 15 16 123 4 pgc p5a pgd pgd = input 0 00 0 0 34 6 5 p10 p5 row-erase time 011 01 0 1 00 12 0 00 16-bit data payload 0 3 0 p5 4-bit command 16-bit data payload 4-bit command ? 2009 microchip technology inc. ds39687e-page 11 pic18f2xjxx/4xjxx family figure 3-4: single row er ase code memory flow done start all rows done? no yes addr = 0 configure device for row erase addr = addr + 1024 start erase sequence and hold pgc high for time p10 pic18f2xjxx/4xjxx family ds39687e-page 12 ? 2009 microchip technology inc. 3.2 code memory programming programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. the write buffer for all devices in the pic18f2xjxx/4xjxx family is 64 bytes. it can be mapped to any 64-byte block beginning at 000000h. the actual memory write sequence takes the contents of this buffer and programs the 64-byte block of code memory indicated by the table pointer. write buffer locations are not cleared following a write operation; the buffer retains its data after the write is complete. this means that the buffer must be written with 64 bytes on each operation. if there are locations in the code memory that are to remain empty, the corresponding locations in the buffer must be filled with ffffh. this avoids rewriting old data from the previous cycle. the programming duration is internally timed. after a start programming command is issued (4-bit com- mand, ? 1111 ?), a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. the code sequence to program a pic18f2xjxx/4xjxx family device is shown in table 3-3. the flowchart shown in figure 3-5 depicts the logic necessary to completely write a pic18f2xjxx/4xjxx family device. the timing diagram that details the start programming command and parameter p9 is shown in figure 3-6. table 3-3: write code memory code sequence note 1: the tblptr register must point to the same region when initiating the program- ming sequence as it did when the write buffers were loaded. 4-bit command data payload core instruction step 1: enable writes. 0000 84 a6 bsf eecon1, wren step 2: load write buffer. 0000 0000 0000 0000 0000 0000 0e ? 2009 microchip technology inc. ds39687e-page 13 pic18f2xjxx/4xjxx family figure 3-5: program code memory flow figure 3-6: table write and start programming instruction timing ( 1111 ) start write sequence all locations done? no done start yes load 2 bytes to write buffer at pic18f2xjxx/4xjxx family ds39687e-page 14 ? 2009 microchip technology inc. 3.2.1 modifying code memory the previous programming example assumed that the device had been bulk erased prior to programming. it may be the case, however, that the user wishes to modify only a section of an already programmed device. the appropriate number of bytes required for the erase buffer must be read out of code memory (as described in section 4.2 ?verify code memory and configura- tion word? ) and buffered. modifications can be made on this buffer. then, the block of code memory that was read out must be erased and rewritten with the modified data. the code sequence is shown in table 3-4. the wren bit must be set if the wr bit in eecon1 is used to initiate a write sequence. 3.2.2 configuration word programming since the flash configuration words are stored in program memory, they are programmed as if they were program data. refer to section 3.2 ?code memory programming? and section 3.2.1 ?modifying code memory? for methods and examples on programming or modifying program memory. see also section 5.0 ?configuration word? for additional information on the configuration words. table 3-4: modifying code memory 4-bit command data payload core instruction step 1: set the table pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0e ? 2009 microchip technology inc. ds39687e-page 15 pic18f2xjxx/4xjxx family 3.3 endurance and retention to maintain the endurance specification of the flash program memory cells, each byte should never be pro- grammed more than once between erase operations. before attempting to modify the contents of a specific byte of flash memory a second time, an erase operation (either a bulk erase or a row erase which includes that byte) should be performed. pic18f2xjxx/4xjxx family ds39687e-page 16 ? 2009 microchip technology inc. 4.0 reading the device 4.1 read code memory code memory is accessed one byte at a time via the 4-bit command, ? 1001 ? (table read, post-increment). the contents of memory pointed to by the table pointer (tblptru:tblptrh:tblptrl) are serially output on pgd. the 4-bit command is shifted in lsb first. the read is executed during the next 8 clocks, then shifted out on pgd during the last 8 clocks, lsb to msb. a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-1). this operation also increments the table pointer by one, pointing to the next byte in code memory for the next read. this technique will work to read any memory in the 000000h to 3fffffh address space, so it also applies to reading the configuration registers. table 4-1: read code memory sequence figure 4-1: table read, post-in crement instruction timing ( 1001 ) 4-bit command data payload core instruction step 1: set table pointer. 0000 0000 0000 0000 0000 0000 0e ? 2009 microchip technology inc. ds39687e-page 17 pic18f2xjxx/4xjxx family 4.2 verify code memory and configuration word the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. because the flash configuration words are stored at the end of program memory, it is verified with the rest of the code at this time. the verify process is shown in the flowchart in figure 4-2. memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer?s buffer. refer to section 4.1 ?read code memory? for implementation details of reading code memory. figure 4-2: verify code memory flow 4.3 blank check the term ?blank check? means to verify that the device has no programmed memory cells. all memories must be verified: code memory and configuration bits. the device id registers (3ffffeh:3fffffh) should be ignored. a ?blank? or ?erased? memory cell will read as a ? 1 ?, so blank checking a device merely means to verify that all bytes read as ffh. the overall process flow is shown in figure 4-3. given that blank checking is merely code verification with ffh expect data, refer to section 4.2 ?verify code memory and configuration word? for implementation details. figure 4-3: blank check flow note: because the flash configuration word contains the device code protection bit, code memory should be verified immedi- ately after writing if code protection is enabled. this is because the device will not be readable or verifiable if a device reset occurs after the flash configuration words (and the cp0 bit) have been cleared. read low byte read high byte does word = expect data? failure, report error all code memory verified? no yes no set tblptr = 0 start yes done with post-increment with post-increment yes no start blank check device is device blank? continue abort pic18f2xjxx/4xjxx family ds39687e-page 18 ? 2009 microchip technology inc. 5.0 configuration word the configuration words of the pic18f2xjxx/4xjxx family devices are implemented as volatile memory registers. all of the configuration registers (config1l, config1h, config2l, config2h, config3l, config3h, config4l and config4h) are automatically loaded following each device reset. the data for these registers is taken from the four flash configuration words located at the end of program memory. configuration data is stored in order, starting with config1l in the lowest flash address and ending with config4h in the highest. the mapping to specific configuration words is shown in table 5-1. users should always reserve these locations for configuration word data and write their application code accordingly. the upper four bits of each flash configuration word should always be stored in program memory as ? 1111 ?. this is done so these program memory addresses will always be ? 1111 xxxx xxxx xxxx ? and interpreted as a nop instruction if they were ever to be executed. because the corresponding bits in the configuration registers are unimplemented, they will not change the device?s configuration. the configuration and device id registers are summarized in table 5-2. a listing of the individual configuration bits and their options is provided in table 5-3. table 5-1: mapping of the flash configuration words to the configuration registers table 5-2: pic18f45j10 family devices: configuration bits and device ids configuration register flash configuration byte (1) configuration register address config1l xff8h 300000h config1h xff9h 300001h config2l xffah 300002h config2h xffbh 300003h config3l xffch 300004h config3h xffdh 300005h config4l (2) xffeh 300006h config4h (2) xfffh 300007h note 1: see table 2-2 for the complete addresses within code space for specific devices and memory sizes. 2: unimplemented in pic18f45j10 family devices. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300000h config1l debug xinst stvren ? ? ? ?wdten 111- ---1 300001h config1h ? (1) ? (1) ? (1) ? (1) ? (2) cp0 ? ? ---- 01-- 300002h config2l ieso fcmen ? ? ?fosc2fosc1fosc0 11-- -111 300003h config2h ? (1) ? (1) ? (1) ? (1) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300005h config3h ? (1) ? (1) ? (1) ? (1) ? ? ?ccp2mx ---- ---1 3ffffeh devid1 (3) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 see table 3fffffh devid2 (3) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 see table legend: - = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 2: this bit should always be maintained at ? 0 ?. 3: devid registers are read-only and c annot be programmed by the user. ? 2009 microchip technology inc. ds39687e-page 19 pic18f2xjxx/4xjxx family table 5-3: pic18f45j10 family devices: bit descriptions bit name configuration words description debug config1l background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug xinst config1l extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) stvren config1l stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled wdten config1l watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) cp0 config1h code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected ieso config2l internal/external oscillator switchover bit 1 = oscillator switchover mode enabled 0 = oscillator switchover mode disabled fcmen config2l fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled fosc2 config2l default oscillator select bit 1 = clock designated by fosc<1:0> is enabled as system clock when osccon<1:0> = 00 0 = intrc is enabled as system clock when osccon<1:0> = 00 fosc<1:0> config2l primary oscillator select bits 11 = ec oscillator, pll enabled and under software control, clko function on osc2 10 = ec oscillator, clko function on osc2 01 = hs oscillator, pll enabled and under software control 00 = hs oscillator wdtps<3:0> config2h watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 ccp2mx config3h ccp2 mux bit 1 = ccp2 is multiplexed with rc1 0 = ccp2 is multiplexed with rb3 pic18f2xjxx/4xjxx family ds39687e-page 20 ? 2009 microchip technology inc. table 5-4: pic18f46j11 and pic18f46j50 family devices: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 300000h config1l debug xinst stvren ? plldiv2 (3) plldiv1 (3) plldiv0 (3) wdten 111- 1111 300001h config1h ? (2) ? (2) ? (2) ? (2) ? (4) cp0 cpdiv1 (3) cpdiv0 (3) ---- 0111 300002h config2l ieso fcmen ? lpt1osc t1dig fosc2 fosc1 fosc0 11-1 1111 300003h config2h ? (2) ? (2) ? (2) ? (2) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300004h config3l dswdtps3 dswdtps2 dswdtps1 dswdtps0 dswdten dsboren rtcosc dswdtosc 1111 1111 300005h config3h ? (2) ? (2) ? (2) ? (2) msspmsk ? ? iol1way ---- 1--1 300006h config4l wpcfg wpend wpfp5 wpfp4 wpfp3 wpfp2 wpfp1 wpfp0 1111 1111 300007h config4h ? (2) ? (2) ? (2) ? (2) ? ? ?wpdis ---- ---1 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0100 00xx legend: x = unknown, u = unchanged, - = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: values reflect the unprogrammed state as received from the factory and following power-on resets. in all other reset states, th e configuration bytes maintain their previously programmed states. 2: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 3: these bits are not implemented in pic18f46j11 family devices. 4: this bit should always be maintained at ? 0 ?. table 5-5: pic18f46j11 and pic18f46j50 family devices: bit descriptions bit name configuration words description debug config1l background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug xinst config1l enhanced instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) stvren config1l stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled plldiv<2:0> (3) config1l pll input divider bits divider must be selected to provide a 4 mhz input into the 96 mhz pll. 111 = no divide ? oscillator used directly (4 mhz input) 110 = oscillator divided by 2 (8 mhz input) 101 = oscillator divided by 3 (12 mhz input) 100 = oscillator divided by 4 (16 mhz input) 011 = oscillator divided by 5 (20 mhz input) 010 = oscillator divided by 6 (24 mhz input) 001 = oscillator divided by 10 (40 mhz input) 000 = oscillator divided by 12 (48 mhz input) wdten config1l watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) cp0 (4) config1h code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f46j11 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. ? 2009 microchip technology inc. ds39687e-page 21 pic18f2xjxx/4xjxx family cpdiv<1:0> (3) config1h cpu system clock selection bits 11 = no cpu system clock divide 10 = cpu system clock divided by 2 01 = cpu system clock divided by 3 00 = cpu system clock divided by 6 ieso config2l (1,2) two-speed start-up (internal/external oscillator switchover) control bit 1 = oscillator switchover mode enabled 0 = oscillator switchover mode disabled fcmen config2l (1,2) fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled lpt1osc config2l (1,2) low-power timer1 oscillator enable bit 1 = timer1 oscillator configured for low-power operation 0 = timer1 oscillator configured for higher power operation t1dig config2l (1,2) secondary clock source t1oscen enforcement bit (1) 1 = secondary oscillator clock source may be selected (osccon <1:0> = 01 ) regardless of t1oscen state 0 = secondary oscillator clock source may not be selected unless t1con <3> = 1 fosc<2:0> config2l (1,2) oscillator selection bits 111 = ec+pll (s/w controlled by pllen bit), clko on ra6 110 = ec oscillator (pll always disabled) with clko on ra6 101 = hs+pll (s/w controlled by pllen bit) 100 = hs oscillator (pll always disabled) 011 = intoscpllo, internal oscillator with pll (s/w controlled by pllen bit), clko on ra6, port function on ra7 010 = intoscpll, internal oscillator with pll (s/w controlled by pllen bit), port function on ra6 and ra7 001 = intosco, internal oscillator, intosc or intrc (pll always disabled), clko on ra6, port function on ra7 000 = intosc, internal oscillator intosc or intrc (pll always disabled), port function on ra6 and ra7 wdtps<3:0> config2h (1,2) watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 table 5-5: pic18f46j11 and pic18f46j50 family devices: bit descriptions (continued) bit name configuration words description note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f46j11 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. pic18f2xjxx/4xjxx family ds39687e-page 22 ? 2009 microchip technology inc. dswtps<3:0> config3l deep sleep watchdog timer postscale select bits the dswdt prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) dswdten config3l deep sleep watchdog timer enable bit 1 = dswdt enabled 0 = dswdt disabled dsboren config3l deep sleep bor enable bit 1 = bor enabled in deep sleep 0 = bor disabled in deep sleep (does not affect operation in non deep sleep modes) rtcosc config3l rtcc reference clock select bit 1 = rtcc uses t1osc/t1cki as reference clock 0 = rtcc uses intrc as reference clock dswdtosc config3l dswdt reference clock select bit 1 = dswdt uses intrc as reference clock 0 = dswdt uses t1osc/t1cki as reference clock msspmsk (1,2) config3h mssp 7-bit address masking mode enable bit 1 = 7-bit address masking mode enable 0 = 5-bit address masking mode enable iol1way config3h iolock bit one-way set enable bit 1 = the iolock bit (ppscon<0>) can be set once, provided the unlock sequence has been completed. once set, the peripheral pin select registers cannot be written to a second time. 0 = the iolock bit (ppscon<0>) can be set and cleared as needed, provided the unlock sequence has been completed wpcfg (4) config4l write/erase protect configuration words page bit (valid when wpdis = 0 ) 1 = configuration words page is not er ase/write-protected unless wpend and wpfp<5:0> settings include the configuration words page 0 = configuration words page is erase/write-protected, regardless of wpend and wpfp<5:0> settings wpend config4l write/erase protect region select bit (valid when wpdis = 0 ) 1 = flash pages, wpfp<5:0> to configurat ion words page, are write/erase-protected 0 = flash pages, 0 to wpfp<5:0> are write/erase-protected table 5-5: pic18f46j11 and pic18f46j50 family devices: bit descriptions (continued) bit name configuration words description note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f46j11 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. ? 2009 microchip technology inc. ds39687e-page 23 pic18f2xjxx/4xjxx family table 5-6: pic18f47j13 and pic18f47j53 fami ly devices: configuration bits and device ids wpfp<5:0> config4l write/erase protect page start/end location bits used with wpend bit to define which pages in flash will be write/erase-protected. wpdis (5) config4h write protect disable bit 1 = wpfp<5:0>, wpend and wpcfg bits ignored; all flash memory may be erased or written 0 = wpfp<5:0>, wpend and wpcfg bits enabled; write/erase-protect active for the selected region(s) dev<2:0> devid1 device id bits used with the dev<10:3> bits in the device id register 2 to identify the part number. rev<4:0> devid1 revision id bits indicate the device revision. dev<10:3> devid2 device id bits used with the dev<2:0> bits in the device id register 1 to identify the part number. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 300000h config1l debug xinst stvren cfgpllen plldiv2 plldiv1 plldiv0 wdten 111- 1111 300001h config1h ? (2) ? (2) ? (2) ? (2) ? (4) cp0 cpdiv1 (3) cpdiv0 (3) ---- 0111 300002h config2l ieso fcmen clkoec soscsel1 soscsel0 fosc2 fosc1 fosc0 1111 1111 300003h config2h ? (2) ? (2) ? (2) ? (2) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300004h config3l dswdtps3 dswdtps2 dswdtps1 dswdtps0 dswdten dsboren rtcosc dswdtosc 1111 1111 300005h config3h ? (2) ? (2) ? (2) ? (2) msspmsk pllsel adcsel iol1way ---- 1111 300006h config4l wpcfg wpfp6 wpfp5 wpfp4 wpfp3 wpfp2 wpfp1 wpfp0 1111 1111 300007h config4h ? (2) ? (2) ? (2) ? (2) ls48mhz (3) ? wpend wpdis ---- 1-11 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0101 10xx legend: x = unknown, u = unchanged, - = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: values reflect the unprogrammed state as received from the factory and following power-on resets. in all other reset states, th e configuration bytes maintain their previously programmed states. 2: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 3: these bits are not implemented in pic18f47j13 family devices. 4: this bit should always be maintained at ? 0 ?. table 5-5: pic18f46j11 and pic18f46j50 family devices: bit descriptions (continued) bit name configuration words description note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f46j11 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. pic18f2xjxx/4xjxx family ds39687e-page 24 ? 2009 microchip technology inc. table 5-7: pic18f47j13 and pic18f47j53 fa mily devices: bit descriptions bit name configuration words description debug config1l background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug xinst config1l enhanced instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) stvren config1l stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled cfgpllen config1l enable pll on start-up bit 1 = pll enabled on start-up. not recommended for low-voltage designs. 0 = pll disabled on start-up. firmware may later enable pll through osctune<6>. plldiv<2:0> config1l 96 mhz pll input divider bits divider must be selected to provide a 4 mhz input into the 96 mhz pll. 111 = no divide ? oscillator used directly (4 mhz input) 110 = oscillator divided by 2 (8 mhz input) 101 = oscillator divided by 3 (12 mhz input) 100 = oscillator divided by 4 (16 mhz input) 011 = oscillator divided by 5 (20 mhz input) 010 = oscillator divided by 6 (24 mhz input) 001 = oscillator divided by 10 (40 mhz input) 000 = oscillator divided by 12 (48 mhz input) wdten config1l watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) cp0 (4) config1h code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected cpdiv<1:0> (3) config1h cpu system clock selection bits 11 = no cpu system clock divide 10 = cpu system clock divided by 2 01 = cpu system clock divided by 3 00 = cpu system clock divided by 6 ieso config2l (1,2) two-speed start-up (internal/external oscillator switchover) control bit 1 = oscillator switchover mode enabled 0 = oscillator switchover mode disabled fcmen config2l (1,2) fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled clkoec config2l ec mode clock output enable bit 1 = clko output signal active on the ra6 pin (ec mode only) 0 = clko output disabled soscsel<1:0> config2l secondary oscillator circuit selection bits 11 = high-power sosc circuit selected 10 = digital input mode (sclki) 01 = low-power sosc circuit selected 00 = reserved note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f47j13 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. 5: not implemented on pic18f47j53 family devices. ? 2009 microchip technology inc. ds39687e-page 25 pic18f2xjxx/4xjxx family fosc<2:0> config2l (1,2) oscillator selection bits 111 = ec+pll (s/w controlled by pllen bit), clko on ra6 110 = ec oscillator (pll always disabled) with clko on ra6 101 = hs+pll (s/w controlled by pllen bit) 100 = hs oscillator (pll always disabled) 011 = intoscpllo, internal oscillator with pll (s/w controlled by pllen bit), clko on ra6, port function on ra7 010 = intoscpll, internal oscillator with pll (s/w controlled by pllen bit), port function on ra6 and ra7 001 = intosco, internal oscillator, intosc or intrc (pll always disabled), clko on ra6, port function on ra7 000 = intosc, internal oscillator intosc or intrc (pll always disabled), port function on ra6 and ra7 wdtps<3:0> config2h (1,2) watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 dswtps<3:0> config3l deep sleep watchdog timer postscale select bits the dswdt prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) dswdten config3l deep sleep watchdog timer enable bit 1 = dswdt enabled 0 = dswdt disabled dsboren config3l deep sleep bor enable bit 1 = bor enabled in deep sleep 0 = bor disabled in deep sleep (does not affect operation in non deep sleep modes) table 5-7: pic18f47j13 and pic18f47j53 family devices: bit descriptions (continued) bit name configuration words description note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f47j13 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. 5: not implemented on pic18f47j53 family devices. pic18f2xjxx/4xjxx family ds39687e-page 26 ? 2009 microchip technology inc. rtcosc config3l rtcc reference clock select bit 1 = rtcc uses t1osc/t1cki as reference clock 0 = rtcc uses intrc as reference clock dswdtosc config3l dswdt reference clock select bit 1 = dswdt uses intrc as reference clock 0 = dswdt uses t1osc/t1cki as reference clock msspmsk (1,2) config3h mssp 7-bit address masking mode enable bit 1 = 7-bit address masking mode enable 0 = 5-bit address masking mode enable pllsel (5) config3h pll selection bit 1 = 4x pll selected 0 = 96 mhz pll selected adcsel config3h adc mode selection bit 1 = 10-bit adc mode selected 0 = 12-bit adc mode selected iol1way config3h iolock bit one-way set enable bit 1 = the iolock bit (ppscon<0>) can be set once, provided the unlock sequence has been completed. once set, the peripheral pin select registers cannot be written to a second time. 0 = the iolock bit (ppscon<0>) can be set and cleared as needed, provided the unlock sequence has been completed wpcfg config4l write/erase protect configuration words page bit (valid when wpdis = 0 ) 1 = configuration words page is not er ase/write-protected unless wpend and wpfp<6:0> settings include the configuration words page 0 = configuration words page is erase/write-protected, regardless of wpend and wpfp<6:0> wpfp<6:0> config4l write/erase protect page start/end location bits used with wpend bit to define which pages in flash will be write/erase-protected. wpend config4h write/erase protect region select bit (valid when wpdis = 0 ) 1 = flash pages, wpfp<6:0> to configurat ion words page, are write/erase-protected 0 = flash pages, 0 to wpfp<6:0> are write/erase-protected wpdis config4h write protect disable bit 1 = wpfp<6:0>, wpend and wpcfg bits ignored; all flash memory may be erased or written 0 = wpfp<6:0>, wpend and wpcfg bits enabled; write/erase-protect active for the selected region(s) ls48mhz (3) config4h system clock selection bit 1 = system clock is expected at 48 mhz, fs/ls usb clken?s divide-by is set to 8 0 = system clock is expected at 24 mhz, fs/ls usb clken?s divide-by is set to 4 dev<2:0> devid1 device id bits used with the dev<10:3> bits in the device id register 2 to identify the part number. rev<4:0> devid1 revision id bits indicate the device revision. dev<10:3> devid2 device id bits used with the dev<2:0> bits in the device id register 1 to identify the part number. table 5-7: pic18f47j13 and pic18f47j53 family devices: bit descriptions (continued) bit name configuration words description note 1: the configuration bits can only be programmed indire ctly by programming the flash configuration word. 2: the configuration bits are reset to ? 1 ? only on v dd reset; it is reloaded with the programmed value at any device reset. 3: these bits are not implemented in pic18f47j13 family devices. 4: once this bit is cleared, all the configuration registers whic h reside in the last page are also protected. to disable code protection, perform an icsp? bulk erase operation. 5: not implemented on pic18f47j53 family devices. ? 2009 microchip technology inc. ds39687e-page 27 pic18f2xjxx/4xjxx family 5.1 device id word the device id word for the pic18f2xjxx/4xjxx family devices is located at 3ffffeh:3fffffh. these read-only bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code protection has been enabled. the process for reading the device ids is shown in figure 5-1. a complete list of device id values for the pic18f2xjxx/4xjxx family is presented in table 5-8. figure 5-1: read device id word flow 5.2 checksum computation the checksum is calculated by summing the contents of all code memory locations and the device configuration words, appropriately masked. the least significant 16 bits of this sum are the checksum. the checksum calculation differs depending on whether or not code protection is enabled. since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. when calculating a checksum by reading a device, the entire code memory can simply be read and summed. the configuration words can always be read. table 5-8: device id value device device id value devid2 devid1 pic18f24j10 1dh 000x xxxx pic18f25j10 1ch 000x xxxx pic18f44j10 1dh 001x xxxx pic18f45j10 1ch 001x xxxx pic18lf24j10 1dh 010x xxxx pic18lf25j10 1ch 010x xxxx pic18lf44j10 1dh 011x xxxx pic18lf45j10 1ch 011x xxxx pic18f25j11 4dh 101x xxxx pic18f24j11 4dh 100x xxxx pic18f26j11 4dh 110x xxxx pic18f45j11 4eh 000x xxxx pic18f44j11 4dh 111x xxxx pic18f46j11 4eh 001x xxxx pic18f24j50 4ch 000x xxxx pic18f25j50 4ch 001x xxxx pic18f26j50 4ch 010x xxxx pic18f44j50 4ch 011x xxxx pic18f45j50 4ch 100x xxxx start set tblptr = 3ffffe done read low byte read high byte with post-increment with post-increment pic18f46j50 4ch 101x xxxx pic18lf2450 4ch 110x xxxx pic18lf25j50 4ch 111x xxxx pic18lf26j50 4dh 000x xxxx pic18lf44j50 4dh 001x xxxx pic18lf45j50 4dh 010x xxxx pic18lf46j50 4dh 011x xxxx pic18lf24j11 4eh 010x xxxx pic18lf25j11 4eh 011x xxxx pic18lf26j11 4eh 100x xxxx pic18lf44j11 4eh 101x xxxx pic18lf45j11 4eh 110x xxxx pic18lf46j11 4eh 111x xxxx pic18f26j13 59h 001x xxxx pic18f27j13 59h 011x xxxx pic18f46j13 59h 101x xxxx pic18f47j13 59h 111x xxxx pic18lf26j13 5bh 001x xxxx pic18lf27j13 5bh 011x xxxx pic18lf46j13 5bh 101x xxxx pic18lf47j13 5bh 111x xxxx pic18f26j53 58h 001x xxxx pic18f27j53 58h 011x xxxx pic18f46j53 58h 101x xxxx pic18f47j53 58h 111x xxxx pic18lf26j53 5ah 001x xxxx pic18lf27j53 5ah 011x xxxx pic18lf46j53 5ah 101x xxxx pic18lf47j53 5ah 111x xxxx table 5-8: device id value (continued) device device id value devid2 devid1 pic18f2xjxx/4xjxx family ds39687e-page 28 ? 2009 microchip technology inc. table 5-9 describes how to calculate the checksum for each device. table 5-9: checksum computation device code protection checksum pic18f24j10 pic18f44j10 off sum[000000:003ff7] + ([003ff8] & e1h) + ([003ff9] & 04h) + ([003ffa] & c7h) + ([003ffb] & 0fh) + ([003ffd] & 01h) on 0000h pic18f24j11 pic18f44j11 off sum[000000:003ff7] + ([003ff8] & e1h) + ([003ff9] & fch) + ([003ffa] & dfh) + ([003ffb] & ffh) + ([003ffc] & ffh) + ([003ffd] & f9h) + ([003ffe] & ffh) + ([003fff] & f1h) on 0000h pic18f24j50 pic18f44j50 off sum[000000:003ff7] + ([003ff8] & efh) + ([003ff9] & ffh) + ([003ffa] & dfh) + ([003ffb] & ffh) + ([003ffc] & ffh) + ([003ffd] & f9h) + ([003ffe] & ffh) + ([003fff] & f1h) on 0000h pic18f25j10 pic18f45j10 off sum[000000:007ff7] + ([007ff8] & e1h) + ([007ff9] & 04h) + ([007ffa] & c7h) + ([007ffb] & 0fh) + ([007ffd] & 01h) on 0000h pic18f25j11 pic18f45j11 off sum[000000:007ff7] + ([007ff8] & e1h) + ([007ff9] & fch) + ([007ffa] & dfh) + ([007ffb] & ffh) + ([007ffc] & ffh) + ([007ffd] & f9h) + ([007ffe] & ffh) + ([007fff] & f1h) on 0000h pic18f25j50 pic18f45j50 off sum[000000:007ff7] + ([007ff8] & efh) + ([007ff9] & ffh) + ([007ffa] & dfh) + ([007ffb] & ffh) + ([007ffc] & ffh) + ([007ffd] & f9h) + ([007ffe] & ffh) + ([007fff] & f1h) on 0000h pic18f26j11 pic18f46j11 off sum[000000:00fff7] + ([00fff8] & e1h) + ([00fff9] & fch) + ([00fffa] & dfh) + ([00fffb] & ffh) + ([00fffc] & ffh) + ([00fffd] & f9h) + ([00fffe] & ffh) + ([00ffff] & f1h) on 0000h pic18f26j50 pic18f46j50 off sum[000000:00fff7] + ([00fff8] & efh) + ([00fff9] & ffh) + ([00fffa] & dfh) + ([00fffb] & ffh) + ([00fffc] & ffh) + ([00fffd] & f9h) + ([00fffe] & ffh) + ([00ffff] & f1h) on 0000h pic18f26j13 pic18f46j13 off sum[000000:00fff7] + ([00fff8] & ffh) + ([00fff9] & fch) +([00fffa] & ffh) + ([00fffb] & ffh) + ([00fffc] & ffh) + ([00fffd] & ffh) + ([00fffe] & bfh) + ([00ffff] & f3h) on 0000h pic18f26j53 pic18f46j53 off sum[000000:00fff7] + ([00fff8] & ffh) + ([00fff9] & ffh) +([00fffa] & ffh) + ([00fffb] & ffh) + ([00fffc] & ffh) + ([00fffd] & fbh) + ([00fffe] & bfh) + ([00ffff] & fbh) on 0000h pic18f27j13 pic18f47j13 off sum[000000:01fff7] + ([01fff8] & ffh) + ([01fff9] & fch) + ([01fffa] & ffh) + ([01fffb] & ffh) + ([01fffc] & ffh) + ([01fffd] & ffh) + ([01fffe] & ffh) + ([01ffff] & f3h) on 0000h pic18f27j53 pic18f47j53 off sum[000000:01fff7] + ([01fff8] & ffh) + ([01fff9] & ffh) + ([01fffa] & ffh) + ([01fffb] & ffh) + ([01fffc] & ffh) + ([01fffd] & fbh) + ([01fffe] & ffh) + ([01ffff] & fbh) on 0000h legend: [a] = value at address a; sum[a:b] = sum of locations a to b inclusive; + = addition; & = bitwise and. all addresses are hexadecimal. ? 2009 microchip technology inc. ds39687e-page 29 pic18f2xjxx/4xjxx family 6.0 ac/dc characteristics timing requirements for program/verify test mode standard operating conditions operating temperature: 25 c is recommended param no. symbol characteristic min max units conditions v ddcore external supply voltage for microcontroller core during programming operations (pic18 lf devices) 2.25 2.75 v (note 1) d111 v dd supply voltage during programming pic18 lf xxjxx v ddcore 3.60 v normal programming (note 2) pic18 f xxj10 2.70 3.60 v pic18 f xxj50 pic18 f xxj11 pic18 f xxj53 pic18 f xxj13 2.35 3.60 v d112 i pp programming current on mclr ?5 a d113 i ddp supply current during programming ? 10 ma d031 v il input low voltage v ss 0.2 v dd v d041 v ih input high voltage 0.8 v dd v dd v d080 v ol output low voltage ? 0.4 v i ol = 3.4 ma @ 3.3v d090 v oh output high voltage 2.4 ? v i oh = -2.0 ma @ 3.3v d012 c io capacitive loading on i/o pin (pgd) ? 50 pf to meet ac specifications c f filter capacitor value on v cap pic18 lf xxjxx 0.1 ? f (note 1) pic18 f xxj10 4.7 18 f pic18fxxj13 pic18fxxj11 pic18fxxj5x 5.4 18 f note 1: external power must be supplied to the v ddcore /v cap pin if the on-chip voltage regulator is disabled. see section 2.1.1 ?pic18f2xjxx/4xjxx/ lf2xjxx/lf4xjxx devices and the on-chip voltage regulator? for more information. 2: v dd must also be supplied to the av dd pins during programming. av dd and av ss should always be within 0.3v of v dd and v ss , respectively. pic18f2xjxx/4xjxx family ds39687e-page 30 ? 2009 microchip technology inc. p1 t r mclr rise time to enter program/verify mode ?1.0 s p2 t pgc serial clock (pgc) period 100 ? ns p2a t pgcl serial clock (pgc) low time 50 ? ns p2b t pgch serial clock (pgc) high time 50 ? ns p3 t set 1 input data setup time to serial clock 20 ? ns p4 t hld 1 input data hold time from pgc 20 ? ns p5 t dly 1 delay between 4-bit command and command operand 50 ? ns p5a t dly 1 a delay between 4-bit command operand and next 4-bit command 50 ? ns p6 t dly 2 delay between last pgc of command byte to first pgc of read of data word 20 ? ns p9 t dly 5 delay to allow block programming to occur 3.4 ? ms pic18f2xj10/pic18f4xj10 1.2 ? ms pic18f2xj11/pic18f4xj11/ pic18f2xj13/pic18f4xj13/ pic18f2xj5x/pic18f4xj5x p10 t dly 6 delay to allow row erase to occur 49 ? ms pic18f2xj10/pic18f4xj10/ pic18f2xj13/pic18f4xj13/ pic18f2xj53/pic18f4xj53 54 ? ms pic18f2xj11/pic18f4xj11/ pic18f2xj50/pic18f4xj50 p11 t dly 7 delay to allow bulk erase to occur 475 ? ms pic18f2xj10/pic18f4xj10/ pic18f2xj13/pic18f4xj13/ pic18f2xj53/pic18f4xj53 524 ? ms pic18f2xj11/pic18f4xj11/ pic18f2xj50/pic18f4xj50 p12 t hld 2 input data hold time from mclr 400 ? s p13 t set 2v dd setup time to mclr 100 ? ns p14 t valid data out valid from pgc 25 ? ns p16 t dly 8 delay between last pgc and mclr 20 ? ns p17 t hld 3mclr to v dd 3? s p19 t key 1 delay from first mclr to first pgc for key sequence on pgd 4?ms p20 t key 2 delay from last pgc for key sequence on pgd to second mclr 50 ? ns 6.0 ac/dc characteristics timing requirements for program/verify test mode (continued) standard operating conditions operating temperature: 25 c is recommended param no. symbol characteristic min max units conditions note 1: external power must be supplied to the v ddcore /v cap pin if the on-chip voltage regulator is disabled. see section 2.1.1 ?pic18f2xjxx/4xjxx/ lf2xjxx/lf4xjxx devices and the on-chip voltage regulator? for more information. 2: v dd must also be supplied to the av dd pins during programming. av dd and av ss should always be within 0.3v of v dd and v ss , respectively. ? 2009 microchip technology inc. ds39687e-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwindr iver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds39687e-page 32 ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09 |
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